top of page
This site was designed with the
.com
website builder. Create your website today.Start Now

PDP-8 on an FPGA IV: Timing Waveforms

These are from the Verilog simulation running on Icarus Verilog and viewed on gtkwave. They may be useful to others developing their own PDP-8's.

Generic Instruction cycle and memory read  (TAD 0034)
TAD 0 1034.gif

The sequence is:

  1. pc => ma (0160)

  2. read instruction at 0160 (1034: TAD 0034) & increment pc

  3. read [0034] into ac (4000)

Memory Write (DCA 0377)
DCA 3377.gif

The sequence is:

  1. pc => ma (0203)

  2. read instruction at 0203 (3377: DCA 0377) & increment pc

  3. write ac (4400) to 0377 and clear ac

Indirect addressing (TAD I 0042)
TAD I 1442.gif

The sequence is:

  1. pc => ma (0401)

  2. read instruction at 0401 (1442: TAD I 0442) & increment pc

  3. read index value from 0042 (0177) into ma

  4. read contents of 0177 (1234) into ac

Auto-indexing (AND I 0010)
AND I 10 0410.gif

The sequence is:

  1. pc => ma (0611)

  2. read instruction at 0611 (0410: AND I 0010) & increment pc

  3. read value from 0010 (0000) and increment it

  4. write 0001 back into 0010

  5. read value from 0001 (5001) into the ac

Microinstructions (CLA CLL CML)
CLA CLL CML 7320.gif

The sequence is:

  1. pc => ma (2353)

  2. read instruction at 2353 (7320: CLA CLL CML) & increment pc

  3. process the RQST1 items (CLA, CLL)

  4. process the RQST2 items (CML)

  5. ac = 7777; link = 1

Interrupt
Interrupt no extended mem.gif

The sequence is:

  1. Interrupts are enabled with opcode 6001 (ION)

  2. the next instruction, 7000 (NOP), finishes before interrupt occurs

  3. interrupt does JSB 0000 (4000) 

  4. return address (2710) is written to location 0000

  5. control transfers to 0001 which contains opcode 5402 (JMP I 0002)

  6. it jumps to (0002) = location 2713

Interrupt with extended memory
Interrupt with extended memory.gif

The sequence is:

  1. Interrupts are enabled with opcode 6001 (ION)

  2. the next instruction, 7200 (CLA), finishes before interrupt occurs

  3. interrupt does JSB 0000 (4000) 

  4. IF and DF are saved to SF

  5. return address (0346) is written to location 0000

  6. control transfers to 0001 which contains opcode 5400 (JMP I 0000) - the typical return from interrupt

  7. it jumps to (0000) = location 0346

bottom of page