PDP-8 on an FPGA IV: Timing Waveforms
These are from the Verilog simulation running on Icarus Verilog and viewed on gtkwave. They may be useful to others developing their own PDP-8's.
Generic Instruction cycle and memory read (TAD 0034)
The sequence is:
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pc => ma (0160)
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read instruction at 0160 (1034: TAD 0034) & increment pc
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read [0034] into ac (4000)
Memory Write (DCA 0377)
The sequence is:
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pc => ma (0203)
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read instruction at 0203 (3377: DCA 0377) & increment pc
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write ac (4400) to 0377 and clear ac
Indirect addressing (TAD I 0042)
The sequence is:
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pc => ma (0401)
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read instruction at 0401 (1442: TAD I 0442) & increment pc
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read index value from 0042 (0177) into ma
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read contents of 0177 (1234) into ac
Auto-indexing (AND I 0010)
The sequence is:
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pc => ma (0611)
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read instruction at 0611 (0410: AND I 0010) & increment pc
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read value from 0010 (0000) and increment it
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write 0001 back into 0010
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read value from 0001 (5001) into the ac
Microinstructions (CLA CLL CML)
The sequence is:
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pc => ma (2353)
-
read instruction at 2353 (7320: CLA CLL CML) & increment pc
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process the RQST1 items (CLA, CLL)
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process the RQST2 items (CML)
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ac = 7777; link = 1
Interrupt
The sequence is:
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Interrupts are enabled with opcode 6001 (ION)
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the next instruction, 7000 (NOP), finishes before interrupt occurs
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interrupt does JSB 0000 (4000)
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return address (2710) is written to location 0000
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control transfers to 0001 which contains opcode 5402 (JMP I 0002)
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it jumps to (0002) = location 2713
Interrupt with extended memory
The sequence is:
-
Interrupts are enabled with opcode 6001 (ION)
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the next instruction, 7200 (CLA), finishes before interrupt occurs
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interrupt does JSB 0000 (4000)
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IF and DF are saved to SF
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return address (0346) is written to location 0000
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control transfers to 0001 which contains opcode 5400 (JMP I 0000) - the typical return from interrupt
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it jumps to (0000) = location 0346